DON27TZ02-NV001 TITLE: Co-Packaged Optics (CPO) for Advanced Cryocooled Electro-Optical/Infrared (EO/IR) Sensors

OUSW (R&E) CRITICAL TECHNOLOGY AREA(S): Quantum and Battlefield Information Dominance (Q-BID)

COMPONENT TECHNOLOGY PRIORITY AREA(S): Integrated Sensing and Cyber;Microelectronics

PROJECTED CMMC LEVEL REQUIREMENT: Level 2 (Self)

OBJECTIVE: Develop and demonstrate innovative Co-Packaged Optics (CPO) architectures and integration techniques for advanced cryocooled Electro-Optical/Infrared (EO/IR) sensor systems that significantly reduce the number of electrical wirebonds, increase bandwidth density, and withstand rugged maritime environments for deployment in advanced sensing and tactical edge computing platforms.

DESCRIPTION: Current Department of the Navy (DON) platforms are generating unprecedented volumes of data via advanced radar, SIGINT, and high-resolution imaging sensors. Processing of this data at the tactical edge requires extreme bandwidth but can consume excessive powers, creating significant thermal and signal integrity bottlenecks [Ref 1]. Specifically, for advanced EO/IR sensors that operate in cryocooled temperatures (e.g., 70-140K), the excessive power required to electrically read out the data, i.e., transmit from cold space and receive in warm space, presents a challenging limitation on the size, weight, and power (SWaP) of an integrated dewar cooler assembly. Fiber optics and photonic integrated circuits (PICs) are key optical readout technologies that can offer extreme bandwidth, low power consumption, and mature fabrication but require integrated packaging solutions for next generation DON systems [Ref 2].

CPO offers an integrated solution that considers both optical and electrical elements in EO/IR sensor design, optimizing performance, reliability, and manufacturability. CPO brings the optical transceiver components directly into the same package as the readout integrated circuit (ROIC). This minimizes the electrical channel length or completely eliminates it with photonic interconnects, fundamentally lowering power consumption (energy per bit) and enabling massive bandwidth scaling [Refs 1-4]. To date, commercial CPO solutions are primarily designed for room temperature, climate-controlled hyperscale SI data centers.

This STTR topic seeks to adapt and innovate current CPO technologies for the stringent Size, Weight, Power, and Cost (SWaP-C) and packaging (cryogenically cooled) constraints of advanced Navy EO/IR sensing platforms. The focus of the topic is on the design and development of a CPO architecture that integrates with the ROIC layer of a typical EO/IR sensor chip assembly, enables high-bandwidth cold to warm readout, and operates in cryocooled temperatures.

Proposals must address critical challenges, including:

1. ROIC compatibility: PIC interconnect architecture that is compatible with conventional analog and mixed-signal digital ROICs designed in <180 nm node foundries, optimal number of fiber outputs to meet total ROIC bandwidth.

2. Thermal Management: Dissipating heat effectively when dense photonics and ROICs are co-located in a cryocooled integrated dewar assembly. Minimize PIC power consumption to less than 20 mW.

3. Power Efficiency: Choice of electrical-optical conversion scheme and minimizing power consumption (e.g., half-wave voltage for EO modulators, Vpi), PIC waveguide propagation loss, PIC to fiber input/output coupling losses, and stray light scatter.

4. Integration & Packaging: Complementary metal–oxide–semiconductor (CMOS)-compatible substrate materials, 2.5D/3D integration techniques, and cost-effective scalable manufacturing processes.

PHASE I: Conduct a feasibility study for a conceptual design of a CPO architecture with full transceiver functionality that addresses the four critical challenges and is tailored for a SWaP-constrained Navy maritime EO/IR sensor system.

• Deliverables: Perform architectural modeling, signal integrity simulations, and thermal/mechanical modeling.

• Metrics: Define target performance metrics, such as energy efficiency (e.g., < 10 fJ/bit), bandwidth (e.g., > 1 Tbps), coupling loss (e.g., < 0.5 dB/fiber connection) and estimated mean time between failures (MTBF) under standard military environmental conditions (e.g., MIL-STD-810H). Prepare a

• Outcome: A comprehensive Phase II development plan that identifies the PIC foundry and packaging facility, including preliminary packaging designs and a proof-of-concept simulation report.

PHASE II: Develop, fabricate, and demonstrate a working CPO prototype based on the Phase I design. Ensure that the

• Deliverables: The prototype shows compatibility with a notional sensor ROIC (i.e., greater than or equal to 640 x 480 Video Graphics Array (VGA) format and less than or equal to 10 um pitch). (Note: The ROIC digital signals can be emulated using a pseudo-random number generator (PRNG).) Demonstrate that the prototype is capable of cryocooled operation with full transceiver functionality, i.e., efficient electrical-optical conversion and transmission from cold space, data transfer through optical fiber, and optical-electrical conversion in warm space.

• Testing: Conduct laboratory testing in a relevant cryogenic environment (70-140K) to validate bandwidth, power/energy efficiency, coupling loss, and bit-error-rate (BER) for the entire transceiver operation. Perform preliminary environmental testing (thermal cycling, vibration) to prove the viability of the optical attachment and packaging under stress.

• Outcome: Deliver the prototype device, test reports, and a Phase III transition plan for integrating the technology into a specific DON system or sensor suite.

PHASE III DUAL USE APPLICATIONS: Transition to Navy maritime sensing program of record and commercial sensing applications.

• DON/DoW Application: Transition the ruggedized CPO technology to military Prime Contractors for integration into maritime Infrared Search and Track (IRST) and airborne Intelligence, Surveillance, and Reconnaissance (ISR) platforms, and mobile command centers requiring high-performance computing (HPC) at the edge.

• Commercial Application: Transition the technology to commercial markets, specifically targeting telecom infrastructure, hyperscale data centers, and Super Intelligence/Machine Learning (SI/ML) compute clusters where thermal efficiency and bandwidth density are highly valued.

REFERENCES:

1. Yi, Y. and Yu, B. "3D Optoelectronics and Co-Packaged Optics: Innovations, Challenges, and Future Trends." IEEE Journal of Selected Topics in Quantum Electronics, vol. 32, no. 2: 3-D Horizons in Photonics: Integrated Circuits, March-April 2026, Art no. 3700515, pp. 1-15. https://doi.org/10.1109/JSTQE.2025.3641790

2. Estrella, S. B. et al. "Cryogenic optical interconnects for infrared sensing applications." 2022 IEEE Research and Applications of Photonics in Defense Conference (RAPID), 2022. https://doi.org/10.1109/RAPID56086.2022.9911270

3. Chen, G.; Wang, G.; Wang, Z. and Wang, L. "Electronic Chip Package and Co-Packaged Optics (CPO) Technology for Modern AI Era: A Review." Micromachines 2025, 16, 431. https://doi.org/10.3390/mi16040431

4. Tian, W.; Hou, H.; Dang, H.; Cao, X.; Li, D.; Chen, S. and Ma, B. "Progress in Research on Co-Packaged Optics." Micromachines 2024, 15, 1211. https://doi.org/10.3390/mi15101211

KEYWORDS: Co-packaged optics; CPO; silicon photonics; interconnects; read out integrated circuit; ROIC; sensors; Electro-Optical/Infrared; EO/IR

TPOC 1: Richard Espinola
richard.l.espinola.civ@us.navy.mil

TPOC 2: Deborah Van Vechten
deborah.vanvechten.civ@us.navy.mil