N25A-T022 TITLE: Photonic Bump Bonds

OUSD (R&E) CRITICAL TECHNOLOGY AREA(S): Advanced Materials;Microelectronics;Space Technology

OBJECTIVE: Develop an enabler of heterogeneous photonic integrated circuits (PICs), the photonic equivalent of an electrical bump bond.

DESCRIPTION: Most radio frequency (RF) photonic components are created in the plane of the thin film substrate in order, or in part, to allow structures to be large in at least 1 dimension to compensate for, e.g., low electron-photon coupling. For optimum performance of any photonic circuit, the constituent components are best made in the material that individually optimizes their performance. Thus, the PIC of greatest application relevance requires moving the optical beams carrying the signals of interest between different chiplets of different chemical composition, lattice structure/spacing, and sometimes different substrates. Various methodologies are at modest TRL levels to interconnect such edge (of chiplet) emitting species including butt free space coupling, microlens, photonic wire bonds, V-grove alignment, and tapered transitions. However, the optical modes are generally very compact within the launching and receiving waveguide structures, so sub-micron 3D alignment of the 2 sides is crucial to the optical insertion loss. The tendency for most epoxy glues holding actual fibers in place to change shape and size (hence torques on fibers) when cured or subjected to temperature excursions is a major issue. Thus, routinely getting the per facet optical loss down below 0.1 dB is so far illusive. However, in the case of VCSELs, which emit light perpendicular to the substrate, the commercial market for high bandwidth data flow through arrays of fibers has driven the development of an interposer technology which can today yield the desired 0.1 dB loss per facet metric. This STTR topic seeks the development of a technique for planar photonic devices to turn their output beams from the in plane to vertical direction so that they can be packaged together in 3D manner, ideally from bumps located within the body of the chiplets, not just along its edges. Such bumps would allow the highest possible performance component chiplets to be combined into the smallest possible finished die, minimizing the discrepancy between today’s extremely dense digital circuits and photonics. The same sort of bumps should be used to provide the multi-chip wiring module using low loss SiN waveguides and normal CMOS interconnects and wiring structures.

PHASE I: During the base, the right angle turn method described in the proposal shall be developed, at least by simulation, to the point where the technical risk of failure is arguably low. A first experimental demonstration is preferred. The non-SiP component can be of any type of functionality, so little effort shall be expended on improving its internal operation. However, the test plan included in the original proposal must explain how the performance of the joint will be quantitively measured. Write the preliminary Phase II proposal. During the Phase I option, if exercised, complete the proof-of-concept demonstration and negotiate the Phase II contract using a technically detailed proposal and clear work plan.

PHASE II: Work to improve the performance and reliability of the demonstrated link method(s). That is, work to improve the yield of joints with insertion losses of less than 0.1 dB, with threshold performance of >85% and objective level of >97% yield. Invent and demonstrate a way to achieve self-alignment of the mating structures. Deliver test articles to government for verification of performance claims.

PHASE III DUAL USE APPLICATIONS: Demonstrate the utility of this packaging technology by integrating a heterogeneous PIC having more than 5 optical components made from more than 2 different materials and relevance to a military function.

Development of a packaging technology with substantially improved internal integration losses will allow planar RF photonic circuits to be sold in a wider array of settings than currently possible. Attention will then be focused on what functional performance the rf photonic circuit can provide, not have to continuously fight with excessively large noise figures created by the floor of the end-to-end insertion losses.

REFERENCES:

1. Samtec. "Optics". https://www.samtec.com/optics/#development-platforms

2. Lomonte, E.; Stappers, M.; Krämer, L. et al. "Scalable and efficient grating couplers on low-index photonic platforms enabled by cryogenic deep silicon etching." Sci Rep 14, 4256 (2024). https://doi.org/10.1038/s41598-024-53975-4

3. Tamir, T. and Peng, S.T. "Analysis and design of grating couplers." Appl. Phys. 14, pp. 235-254 (1977). https://doi.org/10.1007/BF00882729

4. Dirk TAILLAERT, et al. "Grating Couplers for Coupling between Optical Fibers and Nanophotonic Waveguides." Japanese Journal of Applied Physics, Vol. 45, No. 8A, 2006, pp. 6071-6077

KEYWORDS: bump bonds; vertical packaging; heterogeneous integration; 3D packaging; self-alignment; body pads

TPOC 1: Deborah Van Vechten
Email: [email protected]

TPOC 2: James Adleman
Email: [email protected]

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