N251-D06 TITLE: DIRECT TO PHASE II: Tiling Approach to Large Format Focal Plane Arrays

OUSD (R&E) CRITICAL TECHNOLOGY AREA(S): Integrated Sensing and Cyber;Microelectronics

The technology within this topic is restricted under the International Traffic in Arms Regulation (ITAR), 22 CFR Parts 120-130, which controls the export and import of defense-related material and services, including export of sensitive technical data, or the Export Administration Regulation (EAR), 15 CFR Parts 730-774, which controls dual use items. Offerors must disclose any proposed use of foreign nationals (FNs), their country(ies) of origin, the type of visa or work permit possessed, and the statement of work (SOW) tasks intended for accomplishment by the FN(s) in accordance with the Announcement. Offerors are advised foreign nationals proposed to perform on this topic may be restricted due to the technical data under US Export Control Laws.

OBJECTIVE: Develop and demonstrate a focal plane array (FPA) tiling technique that permits small, high-yield FPA and/or read-out integrated circuits (ROIC) chiplets to be assembled into a high-performing, large format FPA having appropriate flatness (or curvature) and uniformity to produce high-quality, wide field-of-view (FOV) imagery with improved manufacturing cost and yield.

DESCRIPTION: FPAs are routinely used in military imaging systems operating in the infrared (IR) spectral bands. Achieving high resolution and wide FOV simultaneously results in competing objectives as high resolution requires many pixels on target, while widening FOV inherently leads to increasing pixel sparsity. FPA technology development is therefore driven to two extremes: smaller pixels to increase resolution and larger array sizes to increase FOV. However, due to the lack of lattice compatibility between crystalline Si-based ROIC and epitaxially grown IR detector materials, the sensing layer and ROIC are currently assembled using indium-based bump-bonding techniques, which become more difficult as pixel size is decreased and array size increased. FPA advancement is further challenged by decreasing ROIC yield with increasing ROIC size due to the exponential increase in fabrication defects with ROIC area. While alternatives to bump-bonding may be found, the ROIC yield challenge continues to impede large FPA development because a multitude of Silicon (Si) wafers must be sacrificed to achieve a few ROICs that meet performance requirements.

To improve ROIC yield, tiling approaches in which high yielding small format ROICs or FPAs are assembled into larger arrays have been suggested for over a decade, but tiling remains largely a concept. The active area of existing ROIC designs is surrounded by peripheral electronics that provide address logic and detector bias voltages. To enable tiling, the peripheral electronics must be relocated to permit high fill-factor assembly, thereby avoiding image artifacts arising from inter-tile gaps. The tiled array must also be highly planar to remain within the depth of focus of the image collection optic. These requirements can potentially be met by 3D electronics integration, which should in principle be easy as the connection involves only Si-based analog and digital layers. The purpose of this Direct-to-Phase-II topic is to develop and demonstrate a prototype process for low-cost, large MWIR FPA and ROIC fabrication with tiling.

PHASE I: For a Direct-to-Phase II topic, the Government expects that the small business has accomplished the following:

• Demonstrated experience in FPA fabrication.

• Developed ROIC designs that enable 2- and/or 4-sided tiling of ROICs or FPAs, such that peripheral electronics have been relocated.

• Developed a tiling technique that enables 2- and/or 4-sided tiling of ROICs or FPAs with sufficient precision to permit inter-tile gaps of < 1 pixel to be

routinely achieved.

• Developed techniques to synchronize tile-based images to form full-frame images.

FEASIBILITY DOCUMENTATION: Offerors interested in participating in Direct to Phase II must include in their response to this topic Phase I feasibility documentation that substantiates the scientific and technical merit and Phase I feasibility described in Phase I above has been met (i.e., the small business must have performed Phase I-type research and development related to the topic NOT solely based on work performed under prior or ongoing federally funded SBIR/STTR work) and describe the potential commercialization applications. The documentation provided must validate that the proposer has completed development of technology as stated in Phase I above. Documentation should include all relevant information including, but not limited to: technical reports, test data, prototype designs/models, and performance goals/results. Work submitted within the feasibility documentation must have been substantially performed by the offeror and/or the principal investigator (PI). Read and follow all of the DoN SBIR 25.1 Direct to Phase II Broad Agency Announcement (BAA) Instructions. Phase I proposals will NOT be accepted for this topic.

PHASE II: The Phase II effort, including the Base and Option periods, should fabricate a fully functional tiled FPA consisting of at least 4 tiles, either in a 2x2 2D tile array or a 1x4 1D tile array mounted on a precision interposer. The preferred detector type is the high operating temperature (HOT) mid-wave infrared (MWIR) strained-layer superlattice (SLS) detector. Individual tiles should consist of NKxMK (for example 2048 x 2048) arrays of 5 micrometer (um) pixels, where N and M are selected to produce maximum tiled FPA yield. It is anticipated that peripheral electronics will be direct-bonded to form a multi-layer 3D integrated stack consisting of the detector layer, analog electronics layer, mixed signal layer, and precision interposer layer, although other designs, such as 1D tile arrays where all peripheral electronics are located on 2 sides, are also of interest. The tiling process can involve assembly of complete FPA tiles on an interposer or the assembly of ROIC tiles followed by bonding of a single, full-size, detector array. The tiled FPA will be fabricated from selected, defect-free individual tiles, as some defective tile yield is expected even for these smaller ROIC units. Importantly, the sensor chip assembly should be thoroughly and quantitatively characterized at ambient and operating temperature for operability, noise, gap widths, planarity, and be ready for camera integration in separate, subsequent testing.) Phase II deliverable will be a prototype camera core (tiled sensor chip assembly) packaged in a test dewar with appropriate optics and control electronics. A final report will include relative design and data package, Manufacturing Readiness Level (MRL) assessment for large format focal plane array producibility, and user’s manual for the prototype camera. The Seminal Transition Event will include an imaging demonstration and will occur at the conclusion of Phase II.

PHASE III DUAL USE APPLICATIONS: Large format FPA arrays are in demand across the Services. Within the Navy, the Shipboard Passive Electro-Optic and Infrared (SPEIR) Program of Record (PoR) has a requirement for wide FOV, high-resolution MWIR sensors for surface ships to which this technology is expected to transition. Successful completion of Phase II is expected to result in Phase III funding to scale up the tiled FPA size, improve manufacturability, and pursue other optimizations. Extensive field testing will be performed in Phase III in relevant environments to demonstrate capability. Successful demonstration of tile-based large array format sensors would benefit and improve camera technologies for the commercial digital photography and computer vision, astrophotography/astronomy, and autonomous navigation markets.

REFERENCES:

1. Fillion, R.; Wojnarowski, R.; Kapusta, C.; Saia, R.; Kwiatkowski. K. and J. Lyke, J. "Advanced 3-D stacked technology." Proceedings of 5th Electronics Packaging Technology Conference, EPTC 2003, Article number 127148, pp. 13 – 18. https://ieeexplore.ieee.org/document/1271482

2. Renault, S.; Berger, F.; Franiatte, R.; Mermin, D. and De Brugiere, B.G. "Packaging of a 25-Tiles Device on Large Dimension AlN Ceramic Substrate Keeping Low Dead Areas and Tight Planarity." 2023 IEEE CPMT Symposium Japan, ICSJ 2023, pp. 69–72. https://journals.scholarsportal.info/details/24758418/v2023inone/69_poa2doldaatp.xml

KEYWORDS: Focal Plane Array (FPA); Tiling; Chiplet; Readout Integrated Circuit (ROIC), Optical Detector Array; Mid-Wave Infrared (MWIR); Infrared; IR

TPOC 1: Richard Espinola
Email: [email protected]

TPOC 2: Myron Pauli
Email: [email protected]

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