Radiation-Hardened Super High Frequency (SHF) Electronics

Navy SBIR 24.2 - Topic N242-102
SSP - Strategic Systems Programs
Pre-release 4/17/24   Opened to accept proposals 5/15/24   Closes 6/12/24 12:00pm ET    [ View Q&A ]

N242-102 TITLE: Radiation-Hardened Super High Frequency (SHF) Electronics

OUSD (R&E) CRITICAL TECHNOLOGY AREA(S): Microelectronics; Quantum Science; Space Technology

The technology within this topic is restricted under the International Traffic in Arms Regulation (ITAR), 22 CFR Parts 120-130, which controls the export and import of defense-related material and services, including export of sensitive technical data, or the Export Administration Regulation (EAR), 15 CFR Parts 730-774, which controls dual use items. Offerors must disclose any proposed use of foreign nationals (FNs), their country(ies) of origin, the type of visa or work permit possessed, and the statement of work (SOW) tasks intended for accomplishment by the FN(s) in accordance with the Announcement. Offerors are advised foreign nationals proposed to perform on this topic may be restricted due to the technical data under US Export Control Laws.

OBJECTIVE: Extend the bandwidth of radiation-hardened electronics into the SHF (3 to 30 GHz) regime. This will enable sensing modalities (e.g., low-Size, Weight, and Power (SWaP) atomic clocks for precision timing) that require higher bandwidth signals than have been achieved in prior rad-hard-designs.

DESCRIPTION: The capabilities of modern electronic systems are enabled in large part by their ability to operate at much higher speeds than their obsolete predecessors. Innovations such as high-speed clocking, input/output (I/O), and data storage and high-bandwidth communication have been made possible as feature sizes on integrated circuits have decreased and operating frequencies have pushed into the GHz radio frequency (RF) range. Reduction to state-of-the-art feature sizes is not possible due to the risk of radiation-induced damage. As a result, rad-hard electronics designs have lagged in their capabilities relative to commercial systems. This has limited the adoption of advanced sensing technologies in strategic applications. As a specific example, low-SWaP atomic clocks, which offer better long-term stability and inherent radiation insensitivity than free-running oscillators, require GHz-modulation of the current driving the clock’s Vertical-cavity Surface-emitting Laser (VCSEL) source [Refs 1, 2]. Until the bandwidth of rad-hard designs is increased, important technologies such as this cannot be leveraged to meet the position, navigation, and timing requirements of the mission.

The purpose of this SBIR topic is to bridge at least a portion of the performance gap between state-of-the-art electronics and rad-hard electronics designs. As a demonstration testbed, performers will design and fabricate a system that includes custom electronics that drive a VCSEL. The system must be capable of modulating the current of a VCSEL at 5 GHz and demonstrate that the system is capable of fully suppressing the carrier frequency. Proposers must provide a detailed justification for why their approach is a viable rad-hard design. It is anticipated that proposed designs will leverage widely-adopted rad-hard application-specific integrated circuit (ASIC) design kits such as the Honeywell HX5000 Standard Cell ASIC Platform (a complementary metal oxide semiconductor (CMOS) silicon-on-insulator technology which is limited to 150 nm feature sizes [Ref 3]), but alternative approaches are welcome if their rad-hardness can be justified.

Work produced in Phase II may become classified. Note: The prospective contractor(s) must be U.S. owned and operated with no foreign influence as defined by 32 U.S.C. § 2004.20 et seq., National Industrial Security Program Executive agent and Operating Manual, unless acceptable mitigating procedures can and have been implemented and approved by the Defense Counterintelligence and Security Agency (DCSA) formerly Defense Security Service (DSS). The selected contractor must be able to acquire and maintain at least a secret level facility and Personnel Security Clearances. This will allow contractor personnel to perform on advanced phases of this project as set forth by DCSA and SSP in order to gain access to classified information pertaining to the national defense of the United States and its allies; this will be an inherent requirement. The selected company will be required to safeguard classified material during the advanced phases of this contract IAW the National Industrial Security Program Operating Manual (NISPOM), which can be found at Title 32, Part 2004.20 of the Code of Federal Regulations.

PHASE I: Deliver a design concept of rad-hard electronics that can drive a VCSEL suitable for D1 spectroscopy of atomic cesium (single-frequency tunable to 894.6 nm) to produce single-mode output and fully suppress its carrier frequency via current modulation. The feasibility must be demonstrated via detailed analysis, modeling, and simulation. This must include the predicted operating parameters that fully suppress the VCSEL carrier with modulation frequencies from 1 to 10 GHz. In addition, a detailed justification must be provided of why the design is expected to demonstrate radiation tolerance up to 300 krad total ionizing dose, which is a specification achieved for advanced timing components (e.g., quartz oscillators) designed for space applications [Ref 4]. The Phase I Option, if exercised, will include the initial design specifications and capabilities description to build a prototype solution in Phase II.

PHASE II: Develop and deliver one (1) prototype system to demonstrate the viability of the Phase 1 rad-hard electronics concept. The design must include the ability to tune the laser temperature, bias current, RF modulation frequency, and RF modulation power. Performers will build a prototype test bed that includes the fabricated electronics and a VCSEL suitable for D1 spectroscopy of atomic cesium (single-frequency, tunable to 894.6 nm). The prototype system must demonstrate full suppression of the VCSEL carrier from 1 to 10 GHz. If this proves unfeasible, a detailed explanation of the limitations and mitigations to ensure future success must be provided. The prototype test bed volume goal of no larger than 10 cm x 10 cm x 3 cm, tight integration of the prototype into a low-SWaP package is not required, but desired. If tight integration is not feasible a detailed path to Phase III integration must be provided. The prototype shall be delivered by the end of Phase II.

PHASE III DUAL USE APPLICATIONS: Integrate the Phase II test bed prototype into a compact unit that provides the ability for a future user to leverage the asset in an atomic clock configuration that is converted for fabrication. It must include the required controls (e.g., connectors, knobs, interfaces) that to allow the user the ability to electronically tune the laser temperature, bias current, RF modulation frequency, and RF modulation power. It must also provide the VCSEL light on an optical output. The integrated unit must retain the 10 cm x 10 cm x 3 cm volume. The integrated system must demonstrate full suppression of the VCSEL carrier from 1 to 10 GHz prior to delivery.

This unit provides an asset that is useful not only for strategic applications, but also for commercial space-based missions requiring radiation hardness.


  1. Lutwak, Robert. "The Chip-scale Atomic Clock – Prototype Evaluation." Proceedings of the 39th Annual Precise Time and Time Interval Meeting, Long Beach, California, November 2007, pp.269-290. https://www.ion.org/publications/abstract.cfm?articleID=10588
  2. "SA.45s CSAC and RoHS CSAC Options 001 and 003." Microchip, 2019. https://ww1.microchip.com/downloads/en/DeviceDoc/00002985.pdf
  3. "HX5000 Standard Cell ASIC Platform." Honeywell, May 2015. https://aerospace.honeywell.com/content/dam/aerobt/en/documents/learn/products/microelectronics/datasheet/HX5000-Datasheet.pdf
  4. "OX-249 Space Qualified Oven Controlled Crystal Oscillator (OCXO)." Microchip, 4/6/2023. https://www.microchip.com/bin/mchp/product-ds.OX-249.pdf

KEYWORDS: Radiation-hardened Electronics; Super High Frequency; Radio Frequency; RF; Chip-scale Atomic Clock; Precision Timing; RF Modulation


The Navy Topic above is an "unofficial" copy from the Navy Topics in the DoD 24.2 SBIR BAA. Please see the official DoD Topic website at www.defensesbirsttr.mil/SBIR-STTR/Opportunities/#announcements for any updates.

The DoD issued its Navy 24.2 SBIR Topics pre-release on April 17, 2024 which opens to receive proposals on May 15, 2024, and closes June 12, 2024 (12:00pm ET).

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Topic Q & A

04/19/24  Q. Can we propose a technology that provides radiation hardness to target electronics?
   A. The topic is to develop custom GHz-speed electronics that are designed to be radiation hard. Technologies that merely mitigate radiation exposure risk (i.e. shielding, etc.), are outside the scope of this topic.

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