N232-090 TITLE: Advanced, RF Transceiver Architecture
OUSD (R&E) CRITICAL TECHNOLOGY AREA(S): Trusted AI and Autonomy
OBJECTIVE: Develop a dynamically reconfigurable, minimal latency and power VPX Digital Signal Processing (DSP) hardware base to simultaneously handle thousands of diverse, possibly overlapping signals for multi-functional situational awareness as part of a high-dynamic range digitized radio frequency (RF) transceiver for multiple Digital Signal Processing capabilities on a single processing card.
DESCRIPTION: Signal intelligence (SIGINT) is the intelligence obtained by the interception of communications and electronic signals. An Electronic Support Measure (ESM) provides the passive capability to search, intercept, collect, classify, geolocate, monitor, copy, exploit, and disseminate these signals over a specific frequency range. A key sub-system to an ESM is the RF transceiver, a single device which transmits and receives with the ability to exploit, RF signals. Current three rack unit (3U) and 6U RF transceivers are limited in the exploitation of the frequency spectrum due to constraints associated with size, weight, power, and cooling (SWaPC) of the associated electronics in the processing of the collected signals.
This topicís goal is to minimize SWaPC and design the ability to increase the signal processing resources of present 3U and 6U RF transceivers. The RF transceiver must be a single processing card while maintaining the following open interface standards:
ANSI / VITA 46.0 VPX Baseline Standard, and ANSI / VITA 48.2 Mechanical Standard for VPX REDI Conduction Cooling.
The RF transceiver must be dynamically reconfigurable via a sensor open systems architecture (SOSA) with defined application programming interfaces (API) for multiple DSP capabilities. The RF transceiver must maintain operating bandwidth throughput without interrupting receive/scan while running complex applications (e.g., emitter isolation and analysis via high-bandwidth processing for signal detection and signal classification). The RF transceiver must maintain high-bandwidth processing throughput without interrupting signal detection/classification when being loaded with complex applications (e.g., not require a reset of electronics or system). The initial design should address the RF transceiverís receiver side noise figure (NF), spurious free dynamic range (SFDR), selectivity, and input third order intercept point (IIP3). In addition, the initial design should address the RF transceiverís transmit side carrier suppression, sideband suppression, output power level, and phase noise. The RF transceiver must have minimal latency while operating over multiple channels. Hardware must be delivered with software and firmware APIs and development kits for rapid integration into U.S. Government labs.
Design tasking in Phase I and Phase II will not be classified. Analysis tasking associated with hardware in Phase II may become classified. Note: The prospective contractor(s) must be U.S. owned and operated with no foreign influence as defined by DoD 5220.22-M, National Industrial Security Program Operating Manual, unless acceptable mitigating procedures can and have been implemented and approved by the Defense Counterintelligence and Security Agency (DCSA) formerly Defense Security Service (DSS). The selected contractor must be able to acquire and maintain a secret level facility and Personnel Security Clearances. This will allow contractor personnel to perform on advanced phases of this project as set forth by DCSA and NAVAIR in order to gain access to classified information pertaining to the national defense of the United States and its allies; this will be an inherent requirement. The selected company will be required to safeguard classified material IAW DoD 5220.22-M during the advanced phases of this contract.
PHASE I: Design and develop an initial RF transceiver solution for airborne platforms in maritime environments including an assessment of the ability of the technology solution (hardware and processing resources) to meet SWaPC form factor as referenced in the Description above. Additional interface requirement documents (ICDs) will be supplied in Phase I. A conceptual architecture of the RF transceiver is required as a product of the Phase I effort. Phase I option should layout initial design requirements for the
(a) operating bandwidth of the RF transceiver,
(b) memory architecture and memory density,
(c) RF transceiverís receiver side NF, SFDR, selectivity, and IIP3,
(d) RF transceiverís transmit side carrier suppression, sideband suppression, output power level, and phase noise, and
(e) (Objective) verification of operational performance requirements through modelling and simulation (M&S) environment.
M & S for performance and SWaPC should be performed, the final report should include the M & S plan and the results of the M & S performed. Include prototype plans to be further developed under Phase II (e.g., associated documentation; i.e., initial block diagram, schematic, capabilities description).
PHASE II: Develop and demonstrate a prototype hardware and firmware solution, or engineering demonstration model (EDM), which builds upon the proposed solution and architecture developed in Phase I with brass-board, proof-of-concept design. A design review should be conducted early in the development phase. The effort shall include a lab demonstration, that is, the prototype hardware should be delivered at the end of Phase II, ready to be tested by the U.S. Government. The final report should include a lab demonstration plan and results, and a transition plan for Phase III focusing on an integration of the RF transceiver, including further technical maturation and manufacturability of the resulting prototype for an airborne military environment.
Work in Phase II may become classified. Please see note in the Description paragraph.
PHASE III DUAL USE APPLICATIONS: Refine the design, and lab (or ground) test, and integrate the RF transceiver solution within a government systems integration lab (SIL), and flight test. If not completed during Phase II, the Phase III design should focus on the manufacturability, production, and sustainment for compliance with the military operating environment (military standards and handbooks such as MIL-STD-810, MIL-STD-704F, MIL-STD-461, MIL-STD-464C should be used as reference until exact specifications are supplied). Phase III deliverables will include documentation not addressed during Phase II such as, but not limited to, Critical Design Review (CDR), associated Qualification Testing and analysis to support Flight Testing, performance requirements, associated ICDs, and manuals.
Dual use in the commercial sector is presently limited; however, some commercial companies are addressing this with the FAA. FedEx is reviewing to install self-defense systems similar to military aircraft and helicopters, and their proposal for anti-missile infrared laser countermeasures to the FAA states "in recent years, in several incidents abroad, civilian aircraft were fired upon by man-portable air defense systems". As missile protection for commercial aircraft continues to be explored, (RF transceivers in) a modified EMS system may be used as an early warning system.
KEYWORDS: Signal Intelligence (SIGINT); (radio frequency) RF Transceiver; ESM (Electronic Support Measures); ANSI/VITA; Digital Signal Processing (DSP); High bandwidth Processing; Hybrid DSP Architectures; Signal Classification; Signal Detection; Spectral Awareness
** TOPIC NOTICE **
The Navy Topic above is an "unofficial" copy from the Navy Topics in the DoD 23.2 SBIR BAA. Please see the official DoD Topic website at www.defensesbirsttr.mil/SBIR-STTR/Opportunities/#announcements for any updates.
The DoD issued its Navy 23.2 SBIR Topics pre-release on April 19, 2023 which opens to receive proposals on May 17, 2023, and closes June 14, 2023 (12:00pm ET).
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|5/26/23||Q.||Can you provide any guidance on requirements, objectives, and/or goals for the number of RF channels per VPX board, instantaneous bandwidth, RF carrier range, and power consumption?|
|A.||Minimum requirements for instantaneous bandwidth, RF carrier range, and RF channels per VPX board will be supplied after the Phase I award. In general, the transceiver will receive approximately 10 separate channels, over a large RF carrier range, varying between narrow and wide instantaneous bandwidths. The mechanical and power requirements are derived from the ANSI / VITA standards in the original topic description (ANSI / VITA 46.0 VPX Baseline Standard; ANSI / VITA 48.2 Mechanical Standard for VPX REDI Conduction Cooling).|