N231-073 TITLE: Radiation Hardened FPGAs for Strategic Systems
OUSD (R&E) CRITICAL TECHNOLOGY AREA(S): Nuclear
The technology within this topic is restricted under the International Traffic in Arms Regulation (ITAR), 22 CFR Parts 120-130, which controls the export and import of defense-related material and services, including export of sensitive technical data, or the Export Administration Regulation (EAR), 15 CFR Parts 730-774, which controls dual use items. Offerors must disclose any proposed use of foreign nationals (FNs), their country(ies) of origin, the type of visa or work permit possessed, and the statement of work (SOW) tasks intended for accomplishment by the FN(s) in accordance with the Announcement. Offerors are advised foreign nationals proposed to perform on this topic may be restricted due to the technical data under US Export Control Laws.
OBJECTIVE: Develop a cost-effective approach to field a radiation-hardened field programmable gate array (FPGA) that can be used in strategic weapons systems.
DESCRIPTION: Strategic Systems Programs (SSP) needs a cost-effective approach to field an FPGA that both address hardware assurance concerns and can meet the objective radiation requirements detailed in request for proposal (RFP) CS-22-1301 to be used in strategic weapons systems [Ref 1]. The current approach to upgrade digital flight hardware electronics for strategic weapon systems involves the redesign of application specific integrated circuits (ASICs) in radiation hardened manufacturing foundries. The full custom nature of the ASIC design addresses assurance concerns by allowing for comprehensive verification to detect bugs and potential hardware Trojans. However, the ASIC design process and requalification of the fabricated ASIC is costly, requires multi-year design and verification cycles and is resource consuming. FPGAs have the ability to shorten the design cycle and provide rapid digital flight hardware electronics upgrade solutions. Unfortunately, no FPGA device currently exists that meets the radiation and assurance requirements to fly in a strategic weapon system.
Currently available FPGA devices and enabling FPGA technology do not meet one or more of the RFP CS-22-1301 objective requirements, such as 300 krad(si) total ionizing dose (TID), single event latchup (SEL) thresholds > 100 MeV-cm2/mg, and device circumvention and recovery (C&R) < 1ms [Ref 1]. These examples are meant to be representative only, and not to be taken as requirements or limits/thresholds. Additionally, hardware assurance concerns exist when using commercial FPGAs in strategic systems as the complete FPGA physical design information has potentially not undergone an independent verification and validation activity by United State Government (USG) to search for bugs and potential hardware Trojans.
The following potential methods may be used to develop solutions to address the above-stated radiation and assurance concerns that currently prohibit the use of FPGAs in strategic weapons systems. This SBIR topic seeks research to further one or more ideas below to address these concerns. Additional solutions provided by the proposers not listed below are welcome as well.
(1) One approach could develop and qualify radiation hardened volatile or non-volatile configuration memory options with transition potential to an FPGA product. Transition paths may include a commercial FPGA vendor or an industrial partner leveraging embedded FPGA (eFPGA) intellectual property (IP) to field an FPGA that meet the objective specifications in RFP# CS-22-1301. These configuration memory options would target an on-shore manufacturing process available from vendors such as Honeywell, Skywater, Intel, and GlobalFoundries.
(2) Another method could involve leveraging existing commercial FPGA physical die. Examples may include upscreening through radiation lot acceptance testing or by developing multi-chip modules with bare commercial FPGA vendor die to meet C&R requirements.
(3) Another acceptable approach could involve a prototype FPGA integrated circuit (IC) design and FPGA software toolchain targeting an onshore manufacturing process that integrates commercially available IP and radiation hardened by design (RHBD) processes. Examples of potential eFPGA IP solutions such as Flexlogic, Avago, and OpenFPGA.
(4) Another acceptable topic could involve developing assurance methods applicable to commercial and open source FPGA devices. These assurance methods would provide a quantitative measure of assurance that the physical FPGA circuitry and FPGA software does not either contain Trojan or bug that could be exploited to cause loss or subversion during operation of the configured FPGA.
The commercial FPGA community categorizes FPGAs in accordance with their configuration memory options. Static random access memory (SRAM)-based configuration memory solutions that enable high performance, but require an off-FPGA configuration file resulting in C&R times > 1ms . FPGAs with embedded non-volatile configuration memory options such as Flash and SONOS meet the objective C&R times but do not meet either TID or SEL objectives [Refs 3, 4].
The proposed R/D effort will develop enabling technology toward fielding an FPGA for a strategic weapon system.
PHASE I: Define and develop the concept(s) and method(s) to further the one of the research areas defined in the Description. Provide description(s) of the approach(es), along with corresponding preliminary evidence supporting each approach. Validate the method selected. Identify technical challenges as well as risks and opportunities for the selected method that will be addressed during Phase II. The Phase I Option, if exercised, will include the initial design specifications and capabilities description to build a prototype and/or a process/tool solution in Phase II. Prepare a Phase II plan.
PHASE II: Develop a physical prototype and/or a process/tool of the proposed concept or method that meets the capabilities listed in the Description. Demonstrate and validate the concept or method. Demonstrate the ability of the prototype and/or a process/tool to meet or exceed the specifications located in the Description. Identify and document any opportunities for improvements for future iterations.
PHASE III DUAL USE APPLICATIONS: Support in transitioning the technology for Navy use in SSP. Support the Navy with transitioning the technology developed within this SBIR topic into a fieldable FPGA that meets the threshold objectives in RFP# CS-22-1301. The RFP# CS-22-1301 government purpose rights (GPR) deliverables will be provided as available materials to realize a fieldable FPGA. Example CS-22-1301 GPR deliverables include pre-silicon IP design files, fabrication-ready GDSII files, and software modules.
The technology developed can also be commercialized into products with space radiation effects requirements. The threshold objectives for space radiation systems is often a subset of the threshold objectives for Strategic Radiation Hard (SRH) systems. Other markets such as automotive/medical with high-reliability and aggressive power-on-reset specifications are other potential candidates for this enabling FPGA technology.
1. "Strategic Radiation Hardened Field Programmable Gate Array." Army Cornerstone Request for Proposal CS-22-1301. https://sam.gov/opp/d8413dd3c00e4128afa03c6888811dd4/view
2. "UltraScale Architecture Configuration User Guide" UG570 (v1.15) September 9, 2021. Xilinx. https://www.xilinx.com/support/documentation/user_guides/ug570-ultrascale-configuration.pdf
3. Wang, J. J., et al., "RADIATION CHARACTERISTICS OF FIELD PROGRAMMABLE GATE ARRAYUSING COMPLEMENTARY-SONOS CONFIGURATION" https://www.microsemi.com/document-portal/doc_view/1244474-rt-polarfire-radiation-test-report
4. N. Rezzak, J.-J. Wang, D. Dsilva and N. Jat, "TID and SEE characterization of Microsemi’s 4th generation radiation tolerant RTG4 flash-based FPGA"
KEYWORDS: FPGA; SRH; strategic; Field Programmable Gate Array; eFPGA; radiation; programmable hardware; strategic system; MRAM; ReRAM; C&R
Communication with SSP TPOCs will be coordinated through the SSP SBIR Program Manager.
TPOC-1: SSP SBIR POC
Email: [email protected]
** TOPIC NOTICE **
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