N231-014 TITLE: Multistatic Radar Network Distributed Time, Frequency, and Phase Synchronization System
OUSD (R&E) CRITICAL TECHNOLOGY AREA(S): Cybersecurity; General Warfighting Requirements (GWR); Networked C3
OBJECTIVE: Develop and demonstrate an adaptive distributed time, frequency, and phase synchronization system having a clock capable of achieving a stability less than 1E-15/sqrt(tau) with flicker floor less than 1E-17 with a 1E-16 long-term stability for a multistatic radar network.
DESCRIPTION: There is a Synthetic Aperture Radar (SAR) network requirement for a precise space-time synchronization system. The stringency of this synchronization requirement tightens with increasing bandwidths and carrier frequencies. Moreover, time errors translate to range errors, and phase and frequency errors negatively affect the Doppler processing and phase coherence. Simple one-way, or standard two-way, time transfer between flying clocks will completely break down because of the time-of-flight variations and Doppler shifts associated with the strongly time-varying link distances. These problems are often approached monolithically and from a monostatic point of view. However, much could be gained by designing these subsystems from a multistatic system�s perspective.
In cases where exploiting bistatic SAR using transmitters of opportunity locating objects of interest in operational theaters without drawing the attention of hostile forces, the limits on time and frequency synchronization may well be set by the radar hardware rather than the method of time transfer. Moreover, the propagation delay from antenna feed to frequency sampling often changes depending on the selected radio frequency (RF) pathway, attenuation or gain, and frequency band. Depending on the RF architecture, this delay may vary by many nanoseconds. Additionally, this delay may drift over the lifetime of the hardware, or due to temperature and internal platform power line variations. Thus, this RF path delay requires continuous calibration to achieve sub-nanosecond timing. Further, the local oscillator carrier is often digitally synthesized, which sets the lower phase noise and spurious limits along with the smallest possible frequency increment. The radar transmission trigger and pulse repetition frequency (PRF) control lines are generally digitally driven (e.g., field-programmable gate array (FPGA)). Such FPGA switching circuitry may have a peak-to-peak jitter as high as 150 ps. Digital devices may also have propagation delays on the order of nanoseconds with the gate-to-gate, and more so, part-to-part, skews of several nanoseconds. Finally, cable lengths of 1 cm amounts to about 51 ps in a RG-58 coax cable. Thus, careful calibration of the RF and digital pathways is required to achieve sub-nanosecond timing. Timing, better than approximately 100 ps, will require an ultra-precise clock operating in femtoseconds. Allowing for 50 ps breakdown in time-of-flight reciprocity, the radar network timescales must be synchronized to less than 1E-15 seconds in time deviation.
Ship defense depends on Doppler radars that detect and track sea-skimming missiles in the ocean clutter. Since the Doppler shift of a fast missile would be far larger than the Doppler shift of known maritime sources of radar clutter, the background noise floor is provided by the phase noise of the local oscillator. Since the radar cross section of an anti-ship missile is very small, detection is difficult. Measurement noise floor analyses revealed excess laser noise to be the dominant performance limitation. Thus, reducing the noise floor is worthwhile in terms of detecting targets with smaller radar cross section at greater ranges. The current instability of microwave stable local oscillators (STLOs) is about 1E-13. Using all-optical clock (1E-16 to 1E-18 inverse square root of the integration time) techniques, a stability improvement of about a factor of 100 should be possible. This should significantly lower the noise background against which sea-skimming missiles need to be detected, and thus improve radar effectiveness in terms of probability of detection and range.
Hence, there is a need for an affordable timing synchronization system with a tactical atomic clock (threshold), and to be later upgraded with a chip-scale photonic integrated clock (Objective). The chip-scale photonic integrated clock for large-scale radar network shall have a stability less than 1E-15/sqrt(tau) with flicker floor less than 1E-17, and with a 1E-16 long-term stability for a multistatic radar network. The tactical atomic clock and the chip-scale photonic integrated clock should be robust, universal, and transfer medium independent. Moreover, either clock should be easy to interface to a wide range of synchronization systems and sensors to suit a variety of networked radar applications. A two-way time transfer scheme is required to null the propagation delay. A holdover capability is highly desirable in case the transfer medium becomes temporarily unavailable. It is further required to have the capability to synchronize using the transmitted radar emissions in absence of a dedicated time transfer medium. Finally, the time and frequency accuracy should match or exceed the limits set by cognitive radar systems used in radar communication networks performing multiple activities and tasks simultaneously.
The timing synchronization system with a tactical atomic clock (threshold), and to be later upgraded with a chip-scale photonic integrated clock (Objective), must be able to operate in the following environments:
(a) Operational Temperature: -40�C�70 �C,
(b) Storage Temperature: -51 �C�85 �C,
(c) Operational Altitude: 0�65,000 ft (0�19,812 m) above sea level,
(d) Mechanical Shock: 40 g, 11 ms, each axis,
(e) Vibration: Tracked and Wheeled Vehicle, Fixed- and Rotary-Wing Aircraft, Unmanned Air vehicles, Gunfire;
(f) Fluid Contaminations: Diesel, Hydraulic, Oil, Bleach;
(g) Relative Humidity: 10�95%
(h) EMI/EMC: MIL-STD-461F, RE102, CE102, CS101, CS114, CS115, CS116, RS103;
(i) Power: MIL-STD-1275E, MIL-STD-704F.
PHASE I: Provide a concept of employment for a timing synchronization system to be an integral part of the radar network using a tactical atomic clock.
Provide a trade-off analysis for a timing synchronization system identifying (1) a tactical atomic clock and a chip-scale photonic integrated clock providing extremely stable timing signals, (2) a radar network signal that needs to be synchronized, (3) a detector that can measure the timing difference between radars, and (4) a control box to lock the timing of all radars to that of the reference. If radars are far away from each other, a timing link is also necessary to deliver the timing signal from each radar in the radar network.
Demonstrate the feasibility of the tactical atomic clock and a chip-scale photonic integrated clock in a synchronization system through modeling and simulation for a bistatic and multistatic radar network. Include the processing blocks that provide the critical functions and include a baseline set of quantitative implementation requirements that will form the basis for further development in Phase II. Provide prototype plans to be developed under Phase II.
PHASE II: Based on the Phase I effort, develop and demonstrate a prototype synchronization system determined to be the most feasible synchronization system for radar networks using a chip-scale photonic integrated clock as specified in the above Description.
Move the synchronization system for radar networks from concept to physical implementation using IEEE 1588v2 Precision Time Protocol where applicable, Network Time Protocol Version 4: Protocol and Algorithms Specification where applicable and 1139-1999 - IEEE Standard Definitions of Physical Quantities for Fundamental Frequency and Time Metrology-Random Instabilities where applicable.
The prototype synchronization system will be tested for performance and environmental stability at a government testing facility during a Rapid Prototype Experimental Demonstration (RPED) to be determined at a future date in Phase II option period, if exercised.
PHASE III DUAL USE APPLICATIONS: Test the adaptive distributed time, frequency, and phase synchronization system having a chip-scale photonic integrated clock, and integrate it into SAR military applications, legacy systems, and other platforms that will benefit from this system. Demonstrate time synchronization capability applications running on a local Area Network (LAN) without external time references. Transition the adaptive distributed time, frequency, and phase synchronization system having a chip-scale photonic integrated clock to a Program of Record.
Military applications for an adaptive distributed time, frequency, and phase synchronization system having a clock include unmanned air systems (UAS), micro-air-vehicles (MAVS), miniature precision-guided weapons, compact high-performance missile- and air-launched interceptors, and advanced laser beam pointing/steering systems in need of: (a) frequency-hopped communications; (b) synchronization and/or syntonization; (c) ranging from precision metrology; and/or (d) Position Navigation Timing (PNT) in Global Positioning System (GPS)-denied environments. Other applications include DoD ground and flight test facilities, data acquisition systems, data fusion, internal aircraft or weapon system networks.
Commercial applications for an adaptive distributed time, frequency, and phase synchronization system having a clock include guidance of airplanes under GPS-denied conditions and navigation in uncharted terrains. Other commercial applications include: all data acquisition systems, LANs, Wide Area Networks, cloud computing, wireless home phone networks using frequency hopping (UWB), and distributed processing applications.
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KEYWORDS: Time; clock; synchronization; multistatic; picosecond; radar
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