Hybrid Packaging of Cryogenic Electronics and Photonic Technologies
Navy STTR 2020.A - Topic N20A-T021
ONR - Mr. Steve Sullivan steven.sullivan@navy.mil
Opens: January 14, 2020 - Closes: February 12, 2020 (8:00 PM ET)

N20A-T021

TITLE: Hybrid Packaging of Cryogenic Electronics and Photonic Technologies

 

TECHNOLOGY AREA(S): Electronics, Information Systems, Sensors

ACQUISITION PROGRAM: IARPA Super Cables and ongoing Darpa MTO whole wafer Multichip modules programs, and CSTG4

OBJECTIVE: The objective of this effort is to originate and begin to mature a scalable heterogeneous packaging plan which results in extreme energy efficiency information transfer at high clock rates and low bit error rate of digital data between superconducting and photonic technologies, each at 4K, in a mechanically robust package that withstands repeated thermal cycling from 300K without performance degradation.

DESCRIPTION: Photonic interconnect has become the dominant technology for long-haul data networks, due to its unmatched distance bandwidth product. As data rates continue to increase, photonic interconnect is being incorporated into room temperature data networks within the equipment racks and even into the multi-chip module packages. This success strongly suggests considering using photonics to move the data created by cryogenic digitizers and sensors up to room temperature and into commercial off-the-shelf (COTS) processors. However, in order for photonic interconnects to become the dominant technology for this application, substantial issues must be addressed. These include the requirements for extreme energy efficiency in getting photons on and off the 4K photonic integrated circuit (PIC) chip and for packaging compatibility with the cryogenic electrically based Very-large-scale integration (VLSI) chips, most of which are based on some form of superconducting device. Most of these superconducting circuits also require magnetic shielding and most shields work by fully encapsulating the circuits, leaving little access for quite rigid and fragile fibers. Moreover, because the power levels required by silicon complementary metal-oxide semiconductor (CMOS) are 4 orders of magnitude larger than needed by niobium digital devices, photonic noise issues that are not problematic at room temperature may have to be addressed when the signal power is drastically reduced, as must occur for low temperature use. Moreover, high frequency circuit operations are a hallmark advantage of superconducting electronics. Thus the packaging that allows transfer of such high speed signals to the PIC requires intimate contact in the photonic to electrical bump bonds to be developed.

Today at 4K isothermal electrical data transport is fully reliable at serial rates above 100 Gbps when the signal path stays on the same chip or moves to an adjacent one through bump bonds and wiring on a Si multi-chip module. The energy cost of such transfer is measured in the aJ/bit. However, electrical data connections between a cryogenic (4K) receiver or processor and one at room temperature introduce significant parasitic heat loads (up to 30mW for 3 bit 40Gps, low BER data flow) given the 4 to 300K thermal gradient and the fundamental physics that connects thermal and electrical conductivity. Thus, the Office of Naval Research (ONR) and the Intelligence Advanced Research Projects Activity (IARPA) are working on high energy efficiency electro-optical modulators/lasers to replace these electrical conductors with optical links. But for them to be successful, the required co-packaging should be considered from the onset, not attempted only at the end. That is the goal of this topic. In future large-scale superconducting circuits, it is already clear the functional blocks will be fabricated on individual chips and those chips pretested. The successful ones will then be flip chip bonded face down on Si multi-chip modules (MCM) which are expected to grow to 300 mm diameter. To function properly, each of the superconducting chips needs to exist where there is a net magnetic field under 4 micro-T in strength. This field will be the sum of the external environmental field (e.g., Earth's) and those generated by currents internal to the vacuum vessel, such as those of the power lines feeding the circuits. To date, that shielding is created passively by closed shields of high permativity magnetic materials around each superconducting processing chip. Thus when providing photonic data links, it is critical to consider the photonic access to the circuits within the magnetic shields as well as to reduce the optical losses in the fiber to waveguide connections. (Any scattered photons will contribute to the parasitic heat load which must be less than the electrical one for photonics to be competitive compared to all electrical data link solutions.)

For small electronics assemblies, it may be feasible to electrically conduct the digital results to the outside edges of the MCM and from there into a specific electro-optical (EO) conversion chip that then launches the light into a fiber. Grating couplers use vertical access for the fiber paths, which may well maximize the chance of breakage in a large area/number of fibers assembly, and currently have about 1 dB of insertion loss. Permanently attached, taped fibers potentially offer lower insertion loss if their movement during epoxy curing, tendency for irreproducible coupling performance, and extreme fragility can be resolved. Both of these methods have problems during cool down with shifting of the alignment of the fiber core with a PIC waveguide. Alignment of arrayed edge couplers after cooling may be more appealing because the planarity of the array can match the array of waveguide inputs. However, no reliable method for optimizing the cold alignment has been invented. Moreover, how this method could scale is totally undefined since the interior superconducting chips currently lack any exposed edges and any mounting areas for attocube-like fiber array aligners.

In all cases, the threshold photonic insertion loss tolerable is 0.2 dB at data rates of 40 Gbps and the goal is to reach below 0.1 dB. The optical alignment and attachment procedures must be robust against thermal cycling (a minimum of 2,000 thermal cycles between 300 to 4K) and vibration of the entire assembly, whether arising from the motion of the deployment platform or created by the periodic motion of a piston within the cryo-cooler compressor. The ability to scale to whole wafer scales and accommodate an arbitrary ratio of superconducting processor area to the numbers of photonic cable leads is desirable. The Navy envisions eventual compatibility with a system geometry where MCM are treated as circuit cards. In this imagination, each MCM is attached on one edge to a thermal bus and staggered about the axis in a deck of card geometry. The perpendicular distance between MCM "cards" must be minimized if the total system density is to be high. How the fibers can attach is then even less clear. Such future enhancements should be compatible with near term choices for the MCM geometry. Phase I proposals must define a plan of attack to demonstrate a packaging strategy for data transmission between a cryogenic superconducting digital integrated circuit (IC) and a room temperature environment. Proposers should clarify the blend of work on total/local magnetic shields versus low loss optical fiber attachment and alignment, all in an MCM context. All blends ranging from 100/0 to 0/100 are acceptable in Phase I. Both sides of this problem must have been worked by the end of Phase II, possibly via a merger of funded efforts in Phase II. A clear Gannt chart of the proposed Phase I Base and Option tasks is essential and should indicate whether the company or non-profit is responsible for each task. Discussion of test plans is desirable. Any need for government furnished property (GFP) should be carefully noted in the proposal.

PHASE I: The Phase I base effort needs to work the efforts defined in the original proposal so as to significantly lower the risk of success if a follow--on award is offered. The provisional Phase II plan delivered at the end of the Base period will determine whether each performer wins a Phase II. If selected, the Phase I Option will then be awarded. It should provide continuity until the Phase II begins and further reduce technical risk of the proposed overall approach. For performers working only one side of the technology in Phase I, Phase II must contain a plan to add the other.

PHASE II: In the Phase II Base period, design, build, and demonstrate a working assembly consisting of a photonically connected (e.g., to the outside world) superconducting MCM at least 10 x 10 mm (preferably larger) in area and having at least 2 distinct magnetically shielded superconducting chips and 2 photonic input/output (IO) links to the MCM. Some interdependence of the functionality of the 2 technologies needs to be demonstrated (e.g., a fiber provides an activation signal to the superconducting chip and its measurement result is conveyed over fiber to room temperature). The insertion losses and heat loads of the design should be quantified by the end of the Base effort. The first Option, if exercised, should further reduce the technical risk to the system performance of the approach taken.

PHASE III DUAL USE APPLICATIONS: As photonic interconnects become the norm at room temperature in data centers and other computationally dense platforms, they need a way to connect without waveform distortion ("robustly") with electronics chips. Even if the systems are run near room temperature, many of the issues are common with those in this STTR topic. These include the need to fit into 3D packages (with no large empty area over the chips, densely placed face down packaging to attach to bump bonds), discrepant wiring line widths/photonic mode diameters, and differential thermal contraction during thermal cycling. Thus, the work in this effort is expected to have applicability in commercial room temperature settings, e.g., within data centers. At low temperatures, success in programs such as IARPA's Super Cables could make sensor array readout for astro-physics and particle physics, where FDM is already the norm, another possible application area. Within the Government, the interests are primarily centered around high-performance computing and radio frequency (RF) digital signal processing. As a subset of the latter, the ability to do analog signal processing within 4K digital receivers is an attractive possibility. Most of these applications are long term, compatible with the philosophy of the STTR program.

REFERENCES:

1. Narayana, S., Semenov, V.K., Polyakov, Y.A., Dotsenko, V. and Tolpygo, S.K. "Design and testing of high-speed interconnects for superconducting multi-chip modules." Superconductor Science And Technology, 25 (2012). https://iopscience.iop.org/article/10.1088/0953-2048/25/10/105012

2. Donley, E.A., Hodby, E., Hollberg, L. and Kitching, J. "Demonstration of high-performance compact magnetic shields for chip-scale atomic devices." REVIEW OF SCIENTIFIC INSTRUMENTS 78, 083102, 2007, DOI: 10.1063/1.2767533. https://pdfs.semanticscholar.org/47ac/742de238c0ece5e91ff7d12c515b9173eb60.pdf

3. Bardalen, Eivind, Akram, Muhammad Nadeem, Malmbekk, Helge and Ohlckers, Per. "Review of Devices, Packaging, and Materials for Cryogenic Optoelectronics." Journal of Microelectronics and Electronic Packaging: October 2015, Vol. 12, No. 4, pp. 189-204. https://www.researchgate.net/publication/287973522_Review_of_Devices_Packaging_and_Materials_for_Cryogenic_Optoelectronics

4. Cardenas, Jaime, Poitras, Carl B., Luke, Kevin, Luo, Lain-Wee, Morton, Paul Adrian and Lipson, Michal. "High Coupling Efficiency Etched Facet Tapers in Silicon Waveguides." IEEE Photonics Technology Letters, Vol. 26, No. 23, December 1, 2014. https://ieeexplore.ieee.org/abstract/document/6895281

5. Son, Gyeongho, Han, Seungjun, Park, Jongwoo, Kwon, Kyungmok and Yu, Kyoungsik “High-efficiency broadband light coupling between optical fibers and photonic integrated circuits.” DeGuyter, Vol. 7, Issue 12, October 20, 2018. DOI: https://doi.org/10.1515/nanoph-2018-0075
https://www.degruyter.com/view/j/nanoph.2018.7.issue-12/nanoph-2018-0075/nanoph-2018-0075.xml

KEYWORDS: Magnetic Shielding; Flip Chip Bonding; Minimal Insertion Loss; Multi-chip Modules; Fiber to Photonic Wave Guide Launches; Coefficient of Thermal Expansion