Quantum Emulation Co-processor Circuit Card
Navy STTR 2020.A - Topic N20A-T016
ONR - Mr. Steve Sullivan [email protected]
Opens: January 14, 2020 - Closes: February 26, 2020 (8:00 PM ET)


TITLE: Quantum Emulation Co-processor Circuit Card


TECHNOLOGY AREA(S): Electronics, Information Systems, Sensors

ACQUISITION PROGRAM: Part of a Technology Candidate effort on Next Generation Signal Processing for undersea systems

OBJECTIVE: Develop and demonstrate a computer co-processor circuit card that allows the computer to emulate the behavior of quantum computer gate operations. The performance threshold of the device is 5 quantum bits (qubits).

DESCRIPTION: Because of their natural parallelism, quantum computers show promise for solving difficult optimization problems related to sensor processing. Quantum computers can be realized using devices that have quantum behavior, such as superconductors and trapped ions. However, the quantum states in such devices can be extremely fragile and are easily affected and contaminated by external disturbances. Therefore, extremely isolated environments, such as cryogenic temperature controls or high-vacuum states, are required and place constraints on their use in shipboard environments. It has been shown that analog-circuit-based emulations can be used to effectively reproduce limited quantum parallelism and that by using existing analog and mixed-signal integrated circuit platforms, an alternative to quantum computing could be possible. The Navy seeks a quantum emulation device that can be integrated as a co-processor into shipboard computing platforms.

PHASE I: Develop a concept for a circuit level simulation platform for the quantum emulation device, and design a 5-qubit quantum emulation device circuit card co-processor such that it is capable of interfacing to a computer using a standard interface, either external (such as Universal Serial Bus) or internal (such as PCI Express). Design a computational benchmark that can be used to evaluate the performance of the quantum emulation device. Develop a Phase II plan.

PHASE II: Undertake fabrication and testing of all components and assemble the 5-qubit quantum emulation device. Conduct benchmark evaluation of the 5-qubit quantum emulation device and document in a final report that includes computational performance, power use, and discusses the computer interface.

PHASE III DUAL USE APPLICATIONS: Execute a plan for extension of the co-processor's capability to 10 qubits or more. Offer this extended qubit co-processor card for use in a variety of Navy applications, with specific uses envisioned for sensor processing, but also for application to a number of commercial computing problems. The 5-qubit device could be offered as a low-cost educational tool for teaching quantum computing methods and for testing quantum computing algorithms.


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KEYWORDS: Quantum Emulation; Sensor Processing; Electronics; Co-processor; Analog Computing; Qubit