High Power Microwave (HPM) Waveform-enhancing Sub-nanosecond Semiconductor Pulse Sharpener
Navy SBIR 2020.1 - Topic N201-074
ONR - Ms. Lore-Anne Ponirakis - loreanne.ponirakis@navy.mil
Opens: January 14, 2020 - Closes: February 12, 2020 (8:00 PM ET)

N201-074

TITLE: High Power Microwave (HPM) Waveform-enhancing Sub-nanosecond Semiconductor Pulse Sharpener

 

TECHNOLOGY AREA(S): Electronics, Materials/Processes, Weapons

ACQUISITION PROGRAM: ONR Code 352: High Power Microwave (HPM) Basic Research

The technology within this topic is restricted under the International Traffic in Arms Regulation (ITAR), 22 CFR Parts 120-130, which controls the export and import of defense-related material and services, including export of sensitive technical data, or the Export Administration Regulation (EAR), 15 CFR Parts 730-774, which controls dual use items. Offerors must disclose any proposed use of foreign nationals (FNs), their country(ies) of origin, the type of visa or work permit possessed, and the statement of work (SOW) tasks intended for accomplishment by the FN(s) in accordance with section 3.5 of the Announcement. Offerors are advised foreign nationals proposed to perform on this topic may be restricted due to the technical data under US Export Control Laws.

OBJECTIVE: Develop an electrically driven, sub-nanosecond, semiconductor pulse sharpener to improve the performance of high power microwave (HPM) pulse generators by reducing/sharpening the rise time of a driving pulse, preserving the trailing edge of the pulse, and increasing the bandwidth of the output.

DESCRIPTION: Wideband (WB) and ultra-wideband (UWB) high power microwave (HPM) source performance parameters can be described in terms of source power or output voltage across a load, pulse repetition rate, pulsewidth, and pulse rise time. When evaluating pulse compression techniques, it is observed that energy density within an inductor is higher than in a capacitor; consequently, the pulsed voltage generated during a short duration at a load may be many times higher than the voltage at which the energy has been stored [Ref 1]. HPM pulse generating sources utilizing inductive storage and discharge techniques to generate high voltage (10s to 100s of kV), at short pulsewidths (~ nanoseconds), are limited in their performance owing to the large trailing edge of the pulse. The performance of HPM pulse generators may be enhanced with the use of a pulse sharpener, which would serve to reduce, or sharpen, the rise time of a driving pulse.   One such device employed for this purpose is the silicon avalanche shaper (SAS), which is a fast closing switch capable of switching high voltage (kV) pulses at sub-nanosecond time scales [Refs 2, 3].

During operation, a SAS diode is initially placed in reverse bias. A fast-rising, high voltage driving pulse (~ kV/ns) applied to the cathode initiates a delayed impact ionization wavefront, which translates to a sharp voltage ramp (kV/ps). One example of SAS construction is a typical p+-n-n+ structure, where the width of the n-base layer is on the order of 100–300 µm. Static breakdown voltages of SAS devices can be on the order of 1 kV for a 1 mm diameter device, but differential voltages (dV/dt) strongly depend on the rise rate of the incident pulse and the material composition (Si, SiC, GaN) [Ref 5].

KEY SEMICONDUCTOR PULSE SHARPENER PARAMETERS
• Sharpen the 10-90% driving pulse rise time from 3-5 ns to < 200 ps, with minimal impact to peak pulse amplitude
• Static Breakdown Voltage, Vbr = 3 kV or higher
• Dynamic Breakdown Voltage = 3 times Vbr
• Differential Voltage Objective: dV/dt  = 200 V/ps
• Differential Voltage Threshold: dV/dt = 20 V/ps
• Diode Restoration Time < 2 µs
• FWHM Switching Time < 300 ps
• Peak Current Rating > 1 kA

PHASE I: Develop a concept for a semiconductor pulse sharpener for sub-nanosecond rise time sharpening of a 3-5 ns driving pulse generated from a HPM inductive storage type pulsed power source. Ensure that the resulting device meets the specific electrical and performance characteristics, and is fabricated in a compact form factor to fit within a constrained operational footprint. Ensure that the contacts of the device are flat, stackable, and solderable, such that multiple wafers can be stacked in series, and parallel, and allow for the addition of heatsinks for thermal management. In addition to electrical and performance characteristics, the device should be analyzed for its thermal properties. Prepare a Phase II plan.

PHASE II: Fabricate single wafer and stacked wafer sub-nanosecond semiconductor pulse sharpeners. Deliver samples to be performance tested. Improvement of key performance parameters such that a pulse output with the 10-90% rise time of a 3-5 ns and a dV/dt of 10 v/ps to a rise time of less than 100ps and a dV/dt of greater than 200 V/ps, while maintaining breakdown voltage, peak pulse amplitude, and compact form factor. Improve device mounts, stacking techniques, and thermal dissipation.

PHASE III DUAL USE APPLICATIONS: Develop manufacturing methods to improve component yield, production time, operational lifetime, and component cost.

Potential applications include: Ultra-wideband radar, Pockels cell drivers, output switches for gas discharge laser systems, perimeter security, and altimeters.

REFERENCES:

1. Brylevsky, V., Efanov, V., Sysyev, A. and Tchashnicov, I. “Power Nanosecond Semiconductor Opening Plasma Switches.”. Ioffe Physical, IEEE 1996. https://ieeexplore.ieee.org/document/564448

2. Grekhov, I. and Mesyats, G. “Physical Basis for High-Power Semiconductor Nanosecond Opening Switches.”,. IEEE Transactions on Plasma Science, Vol 28, No. 5, October 2000. https://ieeexplore.ieee.org/document/901229

3. Focia, R.J., Schamiloglu, E., Fleddermann, C.B., Agee, F.J. and Gaudet, J.
 "Silicon Diodes in Avalanche Pulse-Sharpening Applications." IEEE Transactions on Plasma Science, Vol. 25, No. 2, April 1997. https://ieeexplore.ieee.org/document/602484

4. Merensky, Lev M., Kardo-Sysoev, A.F., Shmilovitz, D. and Kesar, D. “The Driving Conditions for Obtaining Subnanosecond High-Voltage Pulses from a Silicon-Avalanche-Shaper Diode.”, IEEE Transactions on Plasma Science Vol 42, No. 12, December 2014. https://ieeexplore.ieee.org/document/6960896

5. Brylevskiy, V., Smirnova, I., Rozhkov, A., Brunkov, P., Rodin, P. and Grekhov, I. “High-Voltage Subnanosecond Avalanche Sharpening Diodes: A Comparative Study of Silicon and Gallium Arsenide Structures.”, IEEE, 978-1-4799-8402-9, 2015. https://www.researchgate.net/publication/308804557_High-voltage_subnanosecond_avalanche_sharpening_diodes_A_comparative_study_of_silicon_and_gallium_arsenide_structures

6. Arntz, F., Kardo-Sysoev, A. and Krasnykh, A. “SLIM, Short-pulse Technology for High Gradient Induction Accelerators.” SLAC-PUB-13477, December 2008.  https://www.slac.stanford.edu/cgi-wrap/getdoc/slac-pub-13477.pdf

KEYWORDS: Semiconductor Pulse Sharpener; Sub-nanosecond; Semiconductor Avalanche Shaper; SAS; Silicon Avalanche Shaper; Improved Pulse Rise Time; High Power Radio Frequency; HPRF; High Power Microwave; HPM; Wideband; Solid-state; Ultra-Wideband; UWB; Drift Step Recovery Diode; DSRD