DIRECT TO PHASE II - Resilient Tactical Communications Using Interference Mitigation Techniques
Navy SBIR 2019.3 - DIRECT TO PHASE II Topic N193-D03
NAVWAR - Mr. Shadi Azoum - shadi.azoum@navy.mil
Opens: September 24, 2019 - Closes: October 23, 2019 (8:00 PM ET)

N193-D03

TITLE: DIRECT TO PHASE II - Resilient Tactical Communications Using Interference Mitigation Techniques

TECHNOLOGY AREA(S): Air Platform, Battlespace, Electronics

ACQUISITION PROGRAM: Multifunctional Information Distribution System (MIDS) Program of Record, ACAT 1C

The technology within this topic is restricted under the International Traffic in Arms Regulation (ITAR), 22 CFR Parts 120-130, which controls the export and import of defense-related material and services, including export of sensitive technical data, or the Export Administration Regulation (EAR), 15 CFR Parts 730-774, which controls dual use items. Offerors must disclose any proposed use of foreign nationals (FNs), their country(ies) of origin, the type of visa or work permit possessed, and the statement of work (SOW) tasks intended for accomplishment by the FN(s) in accordance with section 3.5 of the Announcement. Offerors are advised foreign nationals proposed to perform on this topic may be restricted due to the technical data under US Export Control Laws.

OBJECTIVE: Develop and demonstrate an Interference Mitigation prototype Very High-Speed Integrated Circuit Hardware Description Language (VHDL) design to operate on Multifunctional Information Distribution System (MIDS) terminals using specified frequencies. Assess design requirements and conduct initial hardware testing and lab demonstration.

DESCRIPTION: The modern communication field is characterized by the networking, Internet Protocol (IP)-ready capability, long range with limited transmit power, high throughput and high Anti-Jam (AJ) resistance. At the same time, Moore's law brought a substantial increase in computational capabilities at the lower power consumption needed for the tactical communications systems, thus making the implementation of these new computationally complex algorithms possible [Ref 1]. However, advancement of increased computational capabilities has also provided the opportunity for adversaries to develop capabilities that can potentially degrade or inhibit communications for military systems on relevant operational environments.

The Navy seeks mature (Technology Readiness Level (TRL) 5 or higher) innovative interference mitigation algorithms solutions that can be implemented in Field Programmable Gated Array (FPGA) to improve communications resilience in a contested/degraded operational environments and demonstrated via a prototype for transition into a MIDS Program Of Record (PoR). The effort should include the assessment of existing software algorithms and should be accompanied by detailed analysis and/or simulations that allow for comparison of performance of the proposed algorithms with current algorithms, and estimates of the computational requirements. The selected interference removal solution(s) should not degrade the link and should demonstrate significant performance during software and hardware simulation, prototyping, and testing. In addition, algorithm parameters should be developed and identified that will be used for a future link layer algorithm that allows for trades to be made between adversarial and friendly nodes to preserve interconnectivity and data dissemination capability. Of higher interest are mature technology solutions (TRL6 or higher) that are efficient in utilization of FPGA resources, have low latency (i.e.,10uS or less) and the ability to separate both signal of interest and interferer, and are able to output both signals.

Work produced in Phase II will likely become classified. Note: The prospective contractor(s) must be U.S. owned and operated with no foreign influence as defined by DoD 5220.22-M, National Industrial Security Program Operating Manual, unless acceptable mitigating procedures can and have been implemented and approved by the Defense Security Service (DSS). The selected contractor and/or subcontractor must be able to acquire and maintain a secret level facility and Personnel Security Clearances, in order to perform on advanced phases of this project as set forth by DSS and SPAWAR in order to gain access to classified information pertaining to the national defense of the United States and its allies; this will be an inherent requirement. The selected company will be required to safeguard classified material IAW DoD 5220.22-M during the advanced phases of this contract. SPAWAR will process the DD254 to support the contractor for personnel and facility certification for secure access.

PHASE I: Feasibility documentation MUST NOT be solely based on work performed under prior or ongoing federally funded SBIR/STTR work. Demonstrating proof of feasibility is a requirement for a Direct to Phase II award.

For this Direct to Phase II topic, the Government expects that the small business would have accomplished the following in a Phase I-type effort:

- Surveyed existing algorithms and established base figure of merits for proposing two algorithms - one implementable in General Purpose Processor (GPP) and another implementable in FPGA.

- Established simulations required to establish the Eb/N0 figure of merit for the proposed algorithm modulations, codeword size and coding rates, included in Additive Gaussian White Noise (AWGN) environments.

FEASIBILITY DOCUMENTATION: Offerors interested in proposing to this Direct to Phase II topic must include in their response Phase I feasibility documentation that substantiates the scientific and technical merit; proof that Phase I feasibility (described in Phase I above) has been met (i.e., the small business must have performed Phase I-type research and development related to the topic, but feasibility documentation must not be solely based on work performed under prior or ongoing federally funded SBIR/STTR work.); and describe the potential commercialization applications. The documentation provided must validate that the proposer has completed Phase I-type development of technology as stated above. Documentation should include all relevant information including, but not limited to: technical reports, test data, prototype designs/models, and performance goals/results. Work submitted within the feasibility documentation must have been substantially performed by the offeror and/or the principal investigator (PI).

PHASE II: Produce, deliver, and implement (in software) prototypes for the proposed algorithms, encompassing both the design of the encoding and decoding algorithms. Conduct evaluations primarily by simulation and testing the algorithms against the required modulations and the emulated threat signal sets. (Note: The Government, at its discretion, may also provide threat signal data for testing. Likewise, the Government may also opt to conduct independent testing at a Government facility at Government expense.) After successful software implementation and performance, integrate proposed algorithms on an actual Software Defined Radio (SDR) hardware to demonstrate successful MIDS Joint Tactical Radio System (JTRS) TRL6 performance on a relevant laboratory environment. Assess FPGA resources required for final integration into targeted SDR FPGA hardware. Evaluate the performance of the algorithms based on efficient utilization of FPGA resources (less than 10%desired), latency (less than 10uSec required), Eb/N0 [Ref 2] and ability to separate both signal of interest and interferer(s) at a TRL6. Prepare a Phase III development plan to transition the technology for Navy and potential commercial use. Partnership with MIDS prime vendors is encouraged.

It is likely that the work under this effort will be classified under Phase II (see Description section for details). Though Phase II work may become classified, the Direct to Phase II proposal will be UNCLASSIFIED.

PHASE III DUAL USE APPLICATIONS: Support the Navy in transitioning the algorithms to Navy use. Further refine finished algorithms to ensure software coded, validated, documented, and information assurance (IA) compliance according to the Phase III development plan for evaluation to determine their figures of merit. Perform test and validation to certify and qualify software and firmware components for Navy use. Implement in the form of fast, efficient algorithms that, once proven, can be coded in software defined radios. Support or license the final product and transition to the Government. Partnership with prime vendors is encouraged.

REFERENCES:

1. J. Proakis and Salehi, M. "Digital Communications, 5th Edition.", McGraw-Hill Education, 2007. https://www.allbookstores.com/Digital-Communications-5th-Edition-John/9780072957167

2. Axford, Roy. "Figures Of Merits (FOMs) for Interference Excision, version 1.0." 13 Jul 2017, SPAWAR PMW/A-170; furnished upon request to topic POC

KEYWORDS: Data Links; Software Defined Radio; Algorithms; Figures of Merits; Interference

TPOC-1: Carlos Alvarado
Phone: 619-524-1582
Email: carlos.alvarado@navy.mil

TPOC-2: Maulin Patel
Phone: 619-252-8077
Email: maulin.patel@navy.mil

 

** TOPIC NOTICE **

These Navy Topics are part of the overall DoD 2019.3 SBIR BAA. The DoD issued its 2019.3 BAA SBIR pre-release on August 23, 2019, which opens to receive proposals on September 24, 2019, and closes October 23, 2019 at 8:00 PM ET.

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