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Analog to Information Processing
Navy SBIR 2016.2 - Topic N162-082 NAVAIR - Ms. Donna Attick - [email protected] Opens: May 23, 2016 - Closes: June 22, 2016 N162-082
TITLE: Analog to Information Processing TECHNOLOGY AREA(S): Electronics, Sensors ACQUISITION PROGRAM: PMA-290 Maritime Surveillance Aircraft The technology within this topic is restricted under the International Traffic in Arms Regulation (ITAR), 22 CFR Parts 120-130, which controls the export and import of defense-related material and services, including export of sensitive technical data, or the Export Administration Regulation (EAR), 15 CFR Parts 730-774, which controls dual use items. Offerors must disclose any proposed use of foreign nationals (FNs), their country(ies) of origin, the type of visa or work permit possessed, and the statement of work (SOW) tasks intended for accomplishment by the FN(s) in accordance with section 5.4.c.(8) of the solicitation. Offerors are advised foreign nationals proposed to perform on this topic may be restricted due to the technical data under US Export Control Laws. OBJECTIVE: Develop an analog to information processing approach to bypass Analog-to-Digital Converter (ADC) that is capable of lower power consumption, smaller circuit size and does not require upfront digitization. DESCRIPTION: The current all-digital processing approach puts the Analog-to-Digital Converter (ADC) and Digital-to-Analog Converter (DAC) as close as possible to the sensors and actuators (antenna, pixels, etc.). This approach has been driven by transistor scaling and programming flexibility. Current performance issues include constraints from power consumption, ADC/DAC requirements, and size. While requirements are application specific, current technologies are constrained by the needed physical size, power consumption, resolution, speed and in some case their cost. Performance of present ADCs generally prohibit the direct digitization of wide bandwidth and high dynamic range RF signals; for example, a 10 GHz bandwidth state-of-the art ADC can provide only 5-bit resolution, while near-term next generation receiver systems would require over 10-bit resolution in the same bandwidth. Based on current trends, this would take approximately 30 years to achieve. The desired innovation is the development of an analog-to-feature converter (AFC) approach that will enable direct conversion of challenging wideband and high dynamic range RF signals to information directly. From a top level functional perspective the AFC should encode the RF/analog input signal to enable a more robust analog representation, i.e., asynchronous pulse domain (continuous-time digital), and to enable implementing general discrete-time/continuous time linear/nonlinear time-frequency filters, delay circuits, and nonlinear processors in the asynchronous pulse domain. The signal path should be split into two after the encoding circuit. The upper path would be used to generate a 1-bit time-frequency map of the input signal using Cohen-class transforms. This map is then optionally delivered to the signal projection unit, analog pre-processing unit, and/or digital post-processing unit, depending upon the tasks the AFC is performing. The key advantages of such an approach is that the analog information to be digitized is highly compressed, and as a result, the AFC requires a much smaller number of ADCs than conventional Nyquist sampling and channelization-based receivers. The key innovation being sought is an implementation approach that accomplishes these functions while significantly reducing the needed size, weight and power required as compared to conventional ADC/DAC approaches. We seek to reduce the computational load on the digital signal processors by an order of magnitude by analog pre-processing of input signal and information and achieve a 10-15 percent reduction in sensor electrical power usage PHASE I: Detail and demonstrate the feasibility and approach through high fidelity simulations. Develop concepts for hardware design and fabrication and provide a means to evaluate the technical feasibility. PHASE II: Based on Phase I effort, further develop designs for a prototype AFC system. Demonstrate performance with respect to wideband radio frequency applications (radar and electronic support measures (ESM)). Describe in detail the system architecture including estimated cost to fully mature this technology and manufacturing approaches. PHASE III DUAL USE APPLICATIONS: Finalize the AFC design and produce a production representative device suitable for use in a next generation maritime surveillance radar and/or ESM system on Navy aircraft. Private Sector Commercial Potential: Commercial data and video systems will be enabled with this technology. REFERENCES:
KEYWORDS: Radar; Analog-to-Digital Converter; Digital-to-Analog Converter; Analog-to-Feature Converter; Information Processing; Sampling Theory
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