Automated Generation of Advanced Test Diagrams to Reduce Test Program Set Life-Cycle Costs Navy SBIR FY2010.1 Sol No.: Navy SBIR FY2010.1 Topic No.: N101-029 Topic Title: Automated Generation of Advanced Test Diagrams to Reduce Test Program Set Life-Cycle Costs Proposal No.: N101-029-2230 Firm: Summit Test Solutions 4266 Linda Vista Dr. Fallbrook, California 92028 Contact: Ronald Taylor Phone: (760) 310-5916 Web Site: http://www.summittests.com Abstract: The objective of this proposal and the proposed research project is to investigate the feasibility of developing a process and associated tools to generate wiring test diagrams automatically using data compliant with the Institute of Electrical and Electronics Engineers (IEEE) Automatic Test Markup Language (ATML) family of standards. Test diagrams show the routing of signals for each test in an automatic test program which tests a Unit Under Test (UUT) from an avionics system or other weapon system on an Automatic Test Equipment (ATE). The test diagrams provide the complete routing of signals from test station instruments to UUT and are a key support document, useful throughout the life cycle of the Test Program Set (TPS). Automated processes for test diagram generation promise to decrease the lengthy time to generate them by eliminating many hours of analysis of test stations, test programs and associated interface hardware. The proposed solution should also enhance the update process and eliminate errors and inconsistencies typical of manually generated diagrams. Relying on the ATML standards for the format of data in this process is a key component of this proposal and will provide a much desired open systems approach. Benefits: When automatic test programs fail to properly test and/or diagnose an avionics UUT, test diagrams are often used by the operator to troubleshoot the TPS and test station. It is essential that the test diagrams are accurate and are consistent with the current test station assets, interface hardware and test program source code. Changes to any of these components often drive the need to update the test diagrams and when generated manually this update process is not always timely or accurate. Without accurate updates, the test diagrams can quickly become outdated and of little value. A process that automates the generation of test diagrams using ATML data can help alleviate these issues. Test diagrams are usually generated after the TPS is integrated and the test program and interface hardware are firm. An automated process will allow test diagrams to be generated prior to integration and could be used to minimize the time to integrate a TPS. When integration changes are made to the test program or interface hardware, the ATML files can be easily updated, then test diagrams automatically regenerated and ready for use. The process and associated tools proposed have commercial applications with all DoD components as well as with the commercial industry. Return