Backend Error-Correction Algorithm Unit for Superconducting ADCS Navy SBIR FY2010.1 Sol No.: Navy SBIR FY2010.1 Topic No.: N101-090 Topic Title: Backend Error-Correction Algorithm Unit for Superconducting ADCS Proposal No.: N101-090-0645 Firm: Physical Optics Corporation Information Technologies Division 20600 Gramercy Place, Bldg. 100 Torrance, California 90501-1821 Contact: Shean McMahon Phone: (310) 320-3088 Web Site: www.poc.com Abstract: To address the Navy's need for real-time error correction (EC) of superconducting analog-to-digital converters (ADCs), Physical Optics Corporation (POC) proposes to develop a new Backend Error-Correction Algorithms Unit for Superconducting ADCs (BECAUS). This proposed technology is based on a suite of blind adaptive EC algorithms implemented on commercially available high-speed semiconductor heterojunction bipolar transistor (HBT) devices. The innovation in BECAUS enables it to perform real-time error correction of systematic and environmental ADC noise sources with data rates up to 20 Gbps and signal bandwidth up to 500 MHz. As a result, BECAUS offers a three-bit improvement in the effective number of bits (ENOB) in a backend EC unit capable of interfacing to room-temperature digital signal processor (DSP) electronics; this directly addresses the PMW-120 requirements for high speed all-digital receivers. In Phase I, POC will demonstrate feasibility of BECAUS by applying software implemented algorithms to recorded data from a Hypres superconducting ADC, and quantify the performance advantage. In Phase II, POC will develop a prototype containing a suite of blind adaptive algorithms, implemented with semiconductor HBT technology. POC will determine bit-level improvement, latency, and power consumption for a 10-MHz sample, and scaling as the ADC bandwidth is increased to 500 MHz. Benefits: To address the Navy's need for real-time error correction (EC) of superconducting analog-to-digital converters (ADCs), Physical Optics Corporation (POC) proposes to develop a new Backend Error-Correction Algorithms Unit for Superconducting ADCs (BECAUS). This proposed technology is based on a suite of blind adaptive EC algorithms implemented on commercially available high-speed semiconductor heterojunction bipolar transistor (HBT) devices. The innovation in BECAUS enables it to perform real-time error correction of systematic and environmental ADC noise sources with data rates up to 20 Gbps and signal bandwidth up to 500 MHz. As a result, BECAUS offers a three-bit improvement in the effective number of bits (ENOB) in a backend EC unit capable of interfacing to room-temperature digital signal processor (DSP) electronics; this directly addresses the PMW-120 requirements for high speed all-digital receivers. In Phase I, POC will demonstrate feasibility of BECAUS by applying software implemented algorithms to recorded data from a Hypres superconducting ADC, and quantify the performance advantage. In Phase II, POC will develop a prototype containing a suite of blind adaptive algorithms, implemented with semiconductor HBT technology. POC will determine bit-level improvement, latency, and power consumption for a 10-MHz sample, and scaling as the ADC bandwidth is increased to 500 MHz. Return